********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*May 26, 2014
*ECN S14-1122, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR644DP D G S 
M1 3 GX S S NMOS W= 11212000u L= 0.25u 
M2 S GX S D PMOS W= 11212000u L= 0.10u 
R1 D 3 1.83e-03 4.226e-03 1.209e-05 
CGS GX S 1.405e-09 
CGD GX D 1.000e-13 
RG G GY 0.70 
RTCV 100 S 1e6 3.680e-04 -8.089e-07 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 11212000u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 7.726e-06 NSUB = 9.1e+16 
+ KAPPA = 1.01e-06 NFS = 1.187e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 5.005e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 8.653e-08 TREF = 25 BV = 41 
+RS = 1.280e-02 N = 1.043e+00 IS = 1.189e-12 
+EG = 1.155e+00 XTI = 1.269e+00 TRS = 2.392e-03 
+CJO = 3.707e-10 VJ = 6.494e+00 M = 5.122e-01 ) 
.ENDS 
